Adaptive CC-CV transition circuit and power management method

ABSTRACT

An adaptive constant current-constant voltage (CC-CV) transition circuit comprises an amplifier, a series-pass device with current sense, a feedback network and a constant current controller to provide a stable and smooth transition between a constant voltage mode and a constant current mode, and vice versa. A voltage regulator loop comprises an amplifier, an optional buffer, a series-pass device with current sense and a feedback network which provides a feedback voltage to the amplifier. A current regulation loop comprises the amplifier, the optional buffer, the series-pass device, the feedback network and a constant current controller comprising a trans-impedence amplifier and a transconductance comparator which generate a current signal to a pseudo-constant bias (PCB) and a voltage signal to the adaptive compensation network (ACN) of the amplifier.

BACKGROUND

This disclosure relates to devices and methods for regulating constantcurrent and constant voltage. More particularly, this disclosure relatesto methods and devices for automatically transitioning between aconstant voltage and a constant current mode.

INTRODUCTION

For a power management unit (PMU), constant voltage (CV) and constantcurrent (CC) methods are employed in order to keep the output load frombeing damaged by over voltage, over current and over power. At the sametime, the PMU can be guaranteed to function within its safety operationarea. CV mode means that the output voltage of the PMU is kept constantunder output load variation, given that output current is less than apre-defined current threshold. CC mode means that the output current ofthe PMU is kept constant under output load variation, given that outputvoltage is less than a pre-defined voltage threshold. It is noted that aPMU is either in CV mode or CC mode during its steady state operation.

Consider an over current scenario, and assume that output of a PMU isshorted to ground while the PMU is in CV mode, the output currentincreases as the PMU is targeted to maintain a constant voltage. Whenthe output current researches a pre-defined current threshold, CC modeis activated. It takes over the control from CV mode and hence outputcurrent is regulated to a target current level. When the output shortcircuit is removed, output voltage ramps up as the excess current flowsto the output node. At the time output voltage is higher than thepre-defined voltage reference, CV mode is activated, it takes over thecontrol from CC mode and hence output voltage is then regulated to thetarget voltage level again. Without CC mode, an uncontrollable largecurrent will pass through the PMU and the load when a short circuitevent occurs, which causes a thermal issue or damage to the PMU androuting traces. There are various methods to implement CV mode and CCmode controllers for a PMU, yet the handover between CV mode and CC modeis seldom discussed.

This disclosure addresses the CV-CC and CC-CV modes handover issue andproposes an architecture that has two distinct features regarding thehandover issue. First, the handover transition speed and stability areoptimized through an adaptive compensation scheme. Second, an amplifieris re-used for both CV and CC modes, which is biased by a unique biasingscheme that also favors handover transition while at the same time,saving silicon area and power consumption. Transistor levelimplementation is proposed as an example to realize the saidarchitecture.

SUMMARY

This disclosure presents an architecture that features stable and smoothtransition between constant voltage and constant current modes and viceversa. System level and transistor level are presented with simulationresults as verification.

A linear regulator comprises an amplifier A₀ having a first and secondinput and an output. The first input connects to V_(FB), the secondinput connects to V_(REF). The amplifier has a pseudo-constant bias(PCB) which, in a CV mode, automatically biases and controls thetransconductance to amplifier A₀ as a function of the operating mode.The amplifier A₀ also has an adaptive compensation network (ACN) whichadaptively alters speed and stability for current regulation in a CCmode. A series-pass device responsive to the amplifier A₀ output and toVDD₂ has an I_(OUT) output and an I_(SEN) output. The series-pass devicecontrols the current from VDD₂ to I_(OUT) and I_(SEN). A feedbacknetwork has two inputs which sense voltage differentials between V_(OUT)and GND and generates an output V_(FB) to amplifier A₀. A CC controllerhas a trans-impedance amplifier Z₁ and a transconductance device Gm₁.The CC controller receives a first input I_(SEN) from the series-passdevice and a second input I_(REF). Amplifier Z₁ compares I_(SEN) andI_(REF) and generates V_(SEL) as voltage for a signal to the ACN foramplifier A₀ and device Gm₁ generates a current control I_(SEL) to thePCB.

A voltage regulation loop to the amplifier A₀ comprises a series-passdevice and a feedback network which applies V_(FB) to the amplifier A₀and a current regulation loop comprises the series-pass device, thefeedback network and the CC controller which applies an I_(SEL) to thePCB and a V_(SEL) to the ACN.

In one embodiment, a buffer is interposed between the amplifier A₀ andthe series-pass device. A compensation capacitor C_(C) is disposed inthe voltage regulation loop and the current regulation loop. In the CVmode, V_(OUT) is regulated, and I_(SEN) is monitored by amplifier Z₁. Inthe CC mode, I_(OUT) is regulated and V_(FB) is monitored by PCB, andwhen V_(FB) ramps up and approaches V_(REF), the regulator is triggeredto implement a CV to CC mode transition.

When the regulator is in a CV mode, the compensation capacitor C_(C) isreduced by the ACN to preserve stability. In CC mode, the CC feedbackloop dominates and the compensation capacitor C_(C) is magnified by theACN for frequency compensation.

In one embodiment, a linear regulator comprises an amplifier A₀ having afirst input and a second input and an output. The first input connectsto V_(FB). The second input connects to V_(REF). The amplifier A₀ has aPCB which automatically biases amplifier A₀ as a function of theoperating mode and has an ACN which adaptively alters speed andstability for current regulation during a CC mode. A buffer connects tothe amplifier A₀ output and generates a buffer output. A series-passdevice is connected to the buffer output and to VDD₂. The series-passdevice has an I_(OUT) output and an I_(SEN) output. The series-passdevice controls the current flowing from VDD₂ to I_(OUT) and I_(SEN).The feedback network has two input voltage which sense differentialbetween V_(OUT) and ground and generates an output voltage feed V_(FB)to amplifier A₀. A CC controller has a transconductance device G_(MI)and has a trans-impedance amplifier Z₁. The controller has a first inputI_(SEN) from the series-pass device and a second input I_(REF). Theamplifier Z₁ compares I_(SEN) and I_(REF), and generates V_(SEL) as avoltage for a signal to the ACN and amplifier A₀. Device G_(MI)generates a current control I_(SEL) to the PCB.

The series-pass device has a current sensor. The series-pass device maycomprise a p-channel MOSFET, an n-channel MOSFET or a bipolar junctiontransistor.

A CV feedback loop to amplifier A₀ operates in a CV mode and a CCfeedback loop to the amplifier A₀ operates in a CC mode.

A compensation capacitor is disposed in the CV feedback loop and the CCfeedback loop. When the regulator is in a CV mode, the compensationcapacitor is reduced by ACN to preserve the stability and in a CC mode,the CC feedback loop dominates and the compensation capacitor ismagnified by the ACN for frequency compensation.

In the CV mode, V_(OUT) is regulated and I_(SEN) is monitored byamplifier Z₁. When the I_(SEN) is larger than I_(REF), the regulatorundergoes a CV to CC mode transition.

A power management method for managing CV-CC and CC-CV transition modein a circuit comprises controlling a CV mode of operation by a firstbias to an amplifier to control transconductance Gm₀ in the amplifier sothat the amplifier has a gain of Gm₀*R₀ to amplify the differencebetween V_(FB) and V_(REF) wherein a CV feedback loop keeps a V_(OUT) toa desired level, and controlling a CC mode of operation by a second biasto the amplifier so that for a second transconductance Gm₁ the amplifierprovides a gain Gm₁*R₀ to amplify the difference between I_(SEN) andI_(REF) wherein a CC feedback loop provides I_(OUT) at a desired level.

The power management method further comprises operating the amplifier ina high gain region in CV and CC modes.

The power management method may also comprise activating a compensationnetwork to the band width for the CC mode and disabling the compensationnetwork in the CV mode.

The power management method may further comprise in the CV moderegulating the V_(OUT) and monitoring the I_(OUT) through the I_(SEN) byan amplifier Z₁ such that when I_(SEN)>I_(REF), the CV mode transitionsto a CC mode.

The power management method may also comprise regulating the I_(OUT) andmonitoring the V_(FB) so that when the V_(FB) ramps up and approachesV_(REF), the CC mode transitions to the CV mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of a linear regulator;

FIG. 2 is a graphical representation of the operating mode for thelinear regulator of FIG. 1;

FIG. 3 is a schematic diagram of a voltage regulator loop for the linearregulator of FIG. 1;

FIG. 4 is a schematic diagram of a current regulation loop for thelinear regulator of FIG. 1;

FIG. 5 is a schematic circuit diagram of a transistor-levelimplementation for a linear regulator; and

FIG. 6 is a graphical representation of a simulator with an outputvoltage of 3V and an over current protection of 100 mA for the linearregulator of FIG. 5.

DETAILED DESCRIPTION

The proposed architecture is demonstrated by a linear regulator 10 asshown in FIG. 1. It illustrates a generalized case wherein thearchitecture can be supplied by a single supply, where VDD₁ equals toVDD₂, or two different supply voltages, VDD₁ and VDD₂, depending on thesystem requirement. V_(OUT) is the regulated output voltage, C_(OUT) isthe output's decoupling capacitor and output load is connected inparallel with C_(OUT). All the node voltages are referred to ground GNDin the following discussion.

The architecture comprises five blocks, namely, amplifier A₀ 20, buffer30, series-pass device with current sense 40, feedback network 50 and CCcontroller 60. The first block is an amplifier, A₀ 20, which has twoinput terminals and one output terminal. One of the inputs is anon-inverting input that connects to feedback voltage, V_(FB), which isgenerated by feedback network. The other input is an inverting inputthat connects to reference voltage, V_(REF), from reference generator,which is not shown in the figure. The output of the amplifier 20 isconnected to a buffer 30. The said amplifier has two special features,Pseudo-Constant Bias (PCB) and Adaptive Compensation Network (ACN). PCBautomatically biases the amplifier 20 and hence controlstransconductance of the amplifier, Gm₀, depending on the operating modeof the linear regulator. ACN adaptively alters speed and stabilitytrade-off for a current regulation loop during the CC mode.

The second block is a buffer 30 that has one input connecting to theoutput of amplifier, A₀, and its output connecting to series-pass device40. The main purpose is to pass the signal at the output of amplifier A₀to the input of series-pass device 40 without degradation. It isolatescapacitive load seen by amplifier A₀ from the series-pass device andenhances driving capability of amplifier A₀. Buffer 30 acts as a leveltranslator in case VDD₁ and VDD₂ have a different potential. The bufferis optional depending upon system requirement. It can be bypassed withthe amplifier A₀ output directly connecting to the input of series-passdevice. It is assumed that the buffer has unity gain in the followingdiscussion.

The third block is a series-pass device with current sense. It has twoinputs; one connects to the buffer output and another one connects tosupply voltage, VDD₂. Series-pass device 40 has two outputs, I_(OUT) andI_(SEN), flowing current output from the block. The series-pass devicecontrols the current flowing from VDD₂ to I_(OUT) and I_(SEN), biased onthe voltage or current signal from the buffer. The series-pass device 40can be implemented by a p-channel or n-channel MOSFET or bipolarjunction transistor. For MOSFET implementation, the output voltagesignal from the buffer is used to alter the amount of current flowthrough the MOSFET from VDD₂. For bipolar junction transistorimplementation, the output current signal from the buffer is used toalter the amount of current through the transistor from VDD₂. The totalcurrent through the series-pass device 40 equals to the sum of I_(OUT)and I_(SEN), wherein I_(OUT) is supplied to the output load and feedbacknetwork, and whereas I_(SEN) is a tracked, scaled down version ofI_(OUT) for modes detection. There are various ways to realize I_(SEN)in the transistor level.

The forth block is feedback network 50 which has of two inputs and oneoutput. The two inputs sense the differential voltage between outputvoltage, V_(OUT), and ground, as demonstrated in FIG. 1. The output offeedback network 50, V_(FB), is a scaled down version of the saiddifferential voltage, which can have different scaling factor based onthe voltage signal's frequency range.

The fifth block is CC controller 60 which has a trans-impedanceamplifier, Z₁, and a transconductance amplifier, G_(MI). The CCcontroller takes two input current signals, I_(SEN) from series-passdevice with current sense and reference current signal, I_(REF). Z₁compares I_(SEN) and I_(REF), and then generates a voltage signal,V_(SEL), which is a voltage control signal for ACN in A₀. V_(SEL) isfurther transformed to current control signal, I_(SEL), for the PCB inA₀.

Working Principle

The proposed architecture in FIG. 1 operates in two modes, namely CVmode and CC mode, depending on loading condition, V_(OUT) and I_(OUT).The operating mode is illustrated in FIG. 2. The y-axis representsoutput voltage of a linear regulator, V_(OUT), whereas the x-axisrepresents output current, I_(OUT). Consider a regulator is set tomaintain V_(OUT) to be V_(TAG) with a maximum output current of I_(TAG).The regulator operates along the lines AB in CV mode, where a voltageregulation loop is dominated. It delivers current to the output load inorder to keep V_(OUT) equal to V_(TAG). When I_(OUT) equals to I_(TAG),CC mode is activated, and a current regulation loop is introduced thatoverpowers the voltage regulation loop in order to keep I_(OUT) equal toI_(TAG). Therefore, the regulator operates along line BC and V_(OUT)drops. When current requested by the load decreases, the regulator'soperating point moves back from C to B as V_(OUT) increases. At the timeV_(OUT) equals to V_(TAG), the current regulation loop passes thecontrol to the voltage regulation loop and hence back to CV mode. Thereis a mode transition or handover from CV to CC mode and from CC to CVmode around point B.

Voltage Regulation Loop

For the proposed architecture, the voltage regulation loop 70 comprisesamplifier A₀ 20, buffer 30, series-pass device with current sense 40 andfeedback network 50, forming a negative feedback loop as shown in FIG.3. The objective of the voltage regulation loop 70 is to maintain V_(FB)to be equal to V_(REF), since V_(FB) is a scaled-down version ofV_(OUT), V_(OUT) is regulated to be approximately

$\begin{matrix}{V_{OUT} = {\left\{ \frac{{Gm}_{0} \times R_{0} \times {Gm}_{pass} \times R_{OUT}}{1 + {\beta \times {Gm}_{0} \times R_{0} \times {Gm}_{pass} \times R_{OUT}}} \right) \times V_{REF}}} & (1)\end{matrix}$

where Gm₀ and R₀ are the transconductance and output impedance of A₀respectively, Gm_(pass) is the transconductance of series-pass device,R_(OUT) is impedance of output load and β is the scaling factor offeedback network. Consider an increase of I_(OUT), V_(OUT) drops andhence V_(FB) drops to be less than V_(REF). A₀ amplifies the error(V_(FB)−V_(REF)) to be V_(AMP) with a gain of Gm₀*R₀. V_(AMP) is givenby equation (2).V _(AMP) =Gm ₀ ×R ₀×(V _(FB) −V _(REF))  (2)

As a result, the series-pass device allows more current to flow fromVDD₂ to V_(OUT), which compensates for the increase of I_(OUT).Therefore, V_(OUT) restores to the targeted value as in equation (1).With a negative feedback loop, frequency compensation is required toensure loop stability. As suggested in FIG. 3, a capacitor, C_(OUT), isplaced at the output of the linear regulator. It introduces a lowfrequency pole as dominant pole and hence stabilizes the negativefeedback loop.

Current Regulation Loop

The current regulation loop 80 comprises amplifier A₀ 20, buffer 30,series-pass device 40 and CC controller 60, forming another negativefeedback loop as shown in FIG. 4. The objective of the currentregulation loop 80 is to maintain I_(SEN) to be equal to I_(REF), sinceI_(SEN) is a scaled-down version of I_(OUT), I_(OUT) is regulated to beapproximately

$\begin{matrix}{I_{OUT} = {\left\{ \frac{Z_{1} \times {Gm}_{1} \times R_{0} \times {Gm}_{pass} \times R_{OUT}}{1 + {M \times Z_{1} \times {Gm}_{1} \times R_{0} \times {Gm}_{pass} \times R_{OUT}}} \right) \times I_{REF}}} & (3)\end{matrix}$

where Z₁ and Gm₁ is the trans-impedance gain and the transconductancegain of CC controller respectively, R₀ is output impedance of A₀,Gm_(pass) is transconductance of series-pass device and M is the scalingratio I_(OUT) to I_(SEN). Consider an increase of I_(OUT), I_(SEN) alsoincreases as it is a scaled-down version of I_(OUT). I_(OUT) is thencompared with I_(SEN) and the difference is converted to voltage signal,V_(SEL), by Z₁. After that, V_(SEL) is transformed to a current signal,I_(SEN) by Gm₁ inside CC controller. I_(SEN) is further amplified byoutput impedance of A₀ to V_(AMP) through PCB and R₀. V_(AMP) is givenby equation (4).V _(AMP) =Gm ₁ ×R ₀ ×Z ₁×(I _(REF) −I _(SEN))  (4)

It is noted that the output impedance stage of A₀, R₀, is re-used incurrent regulation loop. V_(AMP) controls the input of the series-passdevice and allows less current to pass through. Finally, I_(OUT)restores to a targeted value as in equation (3). From a loop stabilityconcern, C_(OUT) does not help stabilizing the loop as V_(OUT) is notused in the current regulation loop. Therefore, a compensationcapacitor, C_(C), is added for frequency compensation. Since C_(C) isalso located inside the voltage regulation loop, it also affectsfrequency compensation of voltage regulation loop. Here, ACN isintroduced to alleviate the stated concern. It adaptively adjusts thevalue of C_(C) base on the operating mode. When the regulator is in CVmode, the voltage regulation loop dominates and then C_(C) is reduced byACN to minimize effect on voltage regulation loop's stability. On theother hand, when the regulator is in CC mode, and current regulationloop dominates, the C_(C) is then magnified by ACN and acts as thedominant role for frequency compensation.

CV-CC Mode Transition

Since there are two different modes for the regulator with two differentloops that control V_(OUT) and I_(OUT) independently, while sharing samecircuit blocks and resources, the mode transition and loop settlingissues must be resolved. The mode transition issue refers to criteria orcondition to switch from CV mode to CC mode and vice versa. The loopsettling issue refers to how to handover from voltage regulation loop inCV mode to current regulation loop in CC mode, such that both loopssettle smoothly and bias correctly and vice versa.

When a regulator is working in CV mode, although the CC controller isnot involved in voltage regulation, it is neither disabled nor shutdown. The CC controller continuously monitors whether I_(SEN) reachesupper bound that is set by I_(REF). Owing to the continuous monitoring,the regulator can detect mode change from CV to CC immediately, that isthe instant when I_(SEN) is larger than or equal I_(REF). Under CV mode,I_(SEN) should be less than I_(REF), and Z₁ acts as a comparator with ahigh bandwidth. V_(SEL) behaves as a digital signal, which is bounded byVDD₁ and GND, and disables the ACN. I_(SEL) also behaves as a digitalsignal, which prevents PCB from changing Gm₀ of A₀. Hence, A₀ functionsas an amplifier that amplifies the error V_(FB)−V_(REF) for voltageregulation with a gain Gm₀*R₀. The output, V_(AMP), controls the amountof current flow through the series-pass device. When I_(OUT) isgradually increased due to load variation, I_(SEN) is also increased andapproaches I_(REF). At the time I_(SEN) is larger than or equal toI_(REF), both V_(SEL) and I_(SEL) flip their state owing to theimpedance gain, Z₁ and transconductance gain Gm₁. The regulator ischanged from CV mode to CC mode, and both ACN and PCB are activated. Itis noted that both V_(SEL) and I_(SEL) behave as an analog signal andcontain the error term, I_(REF)−I_(SEN), as shown in equations (5) and(6).V _(SEL) =Z ₁×(I _(REF) −I _(SEN))  (5)I _(SEL) =Gm ₁ ×Z ₁×(I _(REF) −I _(SEN))  (6)

The error term, I_(REF)−I_(SEN), is used to regulate I_(SEN) and hencecurrent goes into the load, I_(OUT). Since ACN is activated, thecompensation capacitor, C_(C), is magnified and used to compensate thecurrent regulation loop for better stability. PCB is also enabled whichdegenerates the transconductance Gm₀ used in voltage regulation loop. Inaddition, output impedance, R₀, from A₀ is re-used to amplify andconvert I_(SEL) to V_(AMP). Therefore, V_(AMP) adjusts current passingthrough the series-pass device for current regulation. The overall gainfor the current regulation loop is given by equation (7).Gain=Gm ₁ ×R ₀ ×Z ₁  (7)CC-CV Mode Transition

From the CV-CC mode transition, it is observed that the transition istriggered by an over current event, that is, I_(SEN) is larger than orequal to I_(REF). After the transition, the voltage regulation loop issuppressed and the regulator is dominated by the current regulationloop, such that the regulator outputs a regulated current, I_(OUT).

Consider another case when a regulator is working in the CC mode,although amplifier, A₀, does not amplify the voltage error,V_(FB)−V_(REF), it is neither disabled nor shut-down. Owing to theunique bias scheme by PCB, Gm₀ is degenerated and output impedance, R₀,is re-used to amplify I_(SEL). The current regulation loop is stabilizedby C_(C) owing to ACN. Under CC mode, V_(FB) should be less than V_(REF)as the sourcing current by the output load is larger than the sinkingcurrent provided by the series-pass device. With the help of the PCB,the large difference between V_(FB) and V_(REF) does not interfere withV_(AMP), and A₀ is not saturated nor distorted; instead it is maintainedin a high gain operating point. When current drawn by the output load isgradually decreased, V_(OUT) increases as excess current is stored inC_(OUT). At the time V_(FB) ramps up and becomes close to V_(REF), thePCB is deactivated, Gm₀ is regained while Gm₁ is suppressed. As aresult, A₀ amplifies the voltage difference between V_(FB) and V_(REF),the voltage regulation loop takes over the control of the regulator fromthe current regulation loop. I_(OUT) gradually decreases since theregulator tries to regulate V_(OUT) to a desired value. As I_(OUT) andhence I_(SEN) decreases, V_(SEL) flips its state and turns off ACN. As aresult, Z₁ regains its bandwidth and keeps track of I_(SEN) again. Atthis moment, the regulator is back to CV mode. Unlike CV-CC modetransition, the triggering event is determined by V_(OUT), specificallyV_(FB) being larger than V_(REF). Since the mode transitions are basedon two different observations, the regulator will not be tripped in ametastable state, where the regulator's state oscillates between theCV-CC mode transition and the CC-CV mode transition.

Features

As noted, the CV and CC modes are commonly employed in power managementunit. The foregoing disclosure addresses the mode transition issues andemphasizes the stability and smooth transition. The disclosedarchitecture improves CV-CC and CC-CV modes transition with thefollowing three distinct features.

-   -   1. The Pseudo-Constant Bias (PCB) is a controller that provides        proper bias for the amplifier, A₀. In CV mode operation, PCB        provides a bias such that Gm₀ in A₀ comes into effect. As a        result, A₀ has a gain of Gm₀*R₀ to amplify the difference        between V_(FB) and V_(REF). The control is then dominated by the        voltage regulation loop, keeping V_(OUT) to a desired value. In        the CC mode operation, PCB provides another bias condition such        that Gm₀ in A₀ is degenerated. Owing to the unique biasing        scheme, output impedance of A₀, R₀, is re-used with Gm₁ in the        CC controller. This provides a gain of Gm₁*R₀ to amplify the        difference between I_(SEN) and I_(REF) for output current        regulation. It is noted that the amplifier, A₀, is always        operating in high gain region in both the CV and CC modes. This        ensures that A₀ and hence loop gains for both voltage regulation        loop and current regulation loop are high enough to provide a        high accuracy control during the CV-CC and CC-CV mode handover.        It is recalled that the output of A₀, V_(AMP), controls the        series-pass device to adjust current pass through in all modes        and transitions owing to the sharing of output impedance, R₀, by        PCB.    -   2. The Adaptive Compensation Network (ACN) is a controller that        adjusts bandwidth and stability for the current regulation loop.        In the CV mode, ACN disables the compensation network by C_(C)        and hence extends the bandwidth of the current regulation loop;        therefore Z₁ acts as a comparator and V_(SEL) behaves as a        digital signal. This helps the regulator to keep track of        I_(SEN) and responses to over current event immediately. In the        CC mode, ACN is activated, and it magnifies the value of C_(C)        and hence limits the bandwidth of the current regulation loop.        The ACN guarantees a compensated, stabilized negative feedback        loop for current regulation in the CC mode. It is noted that the        CV-CC transition has a fast response as it is desired to stop        over current at once. On the other hand, the CC-CV transition        has a slower response since the CC mode has a limited bandwidth.        This allows a smooth transition from current regulation loop to        voltage regulation loop without any glitches.    -   3. The trigger events for the CV-CC mode and CC-CV mode        transitions are based on two different observations. As a        result, the regulator will not fall into a case that oscillates        between the two transitions. Under the CV mode, V_(OUT) is        regulated and I_(SEN) is monitored by Z₁. When I_(SEN) is larger        than I_(REF), the regulator is triggered and undergoes CV-CC        mode transition and then enter CC mode. Under CC mode, I_(OUT)        is regulated and V_(FB) is monitored by PCB. When V_(FB) ramps        up and approaches V_(REF), the regulator is triggered and        undergoes the CC-CV mode transition and then enters the CV mode.        Transistor-Level Implementation

One embodiment of the transistor-level implementation for the proposedarchitecture as a linear regulator 12 is shown in FIG. 5. The amplifier,A₀, comprises P0, P1, P2, P3, N0, N1, N2 and N3, where Gm₀ is thetransconductance of P0, P1 pair and R₀ is the drain-source impedance ofP3 and N3. The buffer is optional depending upon system requirement. Theseries-pass device with current sense is implemented as a pair ofmatched PMOS, P4 and P5, with a size ratio of M to 1. The amplifier A₂and N8 form a negative loop to track the drain-source voltages of P4 andP5. Since gate-source and drain-source voltages for P4 and P5 arematched, the drain currents are matched with a ratio of M to 1 and draincurrent of P5 is equivalent to I_(SEN). The feedback network is formedby a resistive divider, R₁ and R₂. The CC controller is formed by Z₁ andN7, where Gm₁ is the transconductance of N7.

The Pseudo-Constant Bias (PCB) is formed by N4, N5, N6, N7 and V_(BH).The objective is to bias transistors in A₀ in the CV and CC mode. Gatevoltage and hence drain current of N5 and N7 are controlled by Z₁. N4,N5 and V_(BH) are employed to reduce systematic offset of A₀ due to theintroduction of N5 and N7. V_(BN) is a voltage source that matches withvoltage level high when Z₁ acts a comparator in the CV mode.

Consider the linear regulator 12 in the CV mode wherein V_(SEL) is highlevel and a large drain current can pass through N5 and N7. However, thedrain currents for all transistors in A₀ are limited by I_(BIAS) andhence transconductance of N5 and N7 are degenerated. Thetransconductance from P0, P1 pair is dominant and hence the voltageregulation loop takes over the regulator's control.

Consider the linear regulator 12 in the CC mode. Since source impedancebetween N1, N3 pair and the N0, N2 are imbalanced, hencetransconductance Gm₀ from P0, P1 pair is then degenerated. As a result,Gm₁ from N7 is dominant and the current regulation loop comes intoeffect. The output impedance by P3 and N3 amplifies V_(SEL) to V_(AMP)which re-uses the same transistors in A₀ for silicon area and powersaving. It is noted that P0, P1, P2, N0, N1, N2 and I_(BIAS) coupleV_(SEL) to the gate of P3, forming a push-pull output stage. It is alsonoted that owing to the high loop gain, drain current of P3, N3 areforced to be the same, meaning that four branch currents, with N4, N5,N6 and N7 at the bottom, are forced to be the same. This enforces A₀ tostay in high gain region in both the CC and CV mode.

The Adaptive Compensation Network (ACN) comprises N3, N7, P3, buffer(optional) and C_(C). The objective is to magnify the capacitance C_(C)in the loop transfer function depending on the operating mode. In the CVmode, the capacitance of C_(C) is the same as its physical value. In theCC mode, the effective capacitance of C_(C) is amplified by a gain ofGm₁*R₀ due to the Miller effect. Due to the Miller effect, the currentregulation loop is compensated.

Simulation Results

The transistor-level embodiment of linear regulator 12 in FIG. 5 isverified by simulation. A linear regulator with output voltage of 3V andover current protection of 100 mA is designed. FIG. 6 shows thesimulation results. VDD is the supply voltage of the regulator, V_(OUT)is the output voltage of the regulator, IDD is the supply current thatsinks from VDD. V_(SEL) is the internal node voltage in the CCcontroller. From time=0 ms to 4 ms, VDD and hence V_(OUT) ramp up. Fromtime=4 ms to 25 ms, V_(OUT) is regulated to the desired value, and theregulator is in CV mode. At time=25 ms, the output is suddenly shortedto ground. IDD is limited to 100 mA and V_(OUT) is discharged. Theregulator enters CC mode so that V_(SEL) is set to a low voltage. Attime=50 ms, the short circuit load is released, the regulator is stilloperating in CC mode. From time=50 ms to 54 ms, IDD is held at 100 mAand the excess current is used to charge up output capacitor. WhenV_(OUT) is close to 3V, the regulator switched back to CV mode andV_(SEL) is pulled high at the same time.

While preferred embodiments of the foregoing have been set forth forpurposes of illustration, the foregoing description should not be deemeda limitation of the invention herein. Accordingly, variousmodifications, adaptations and alternatives may occur to one skilled inthe art without departing from the spirit and the scope of the presentinvention.

The invention claimed is:
 1. A linear regulator which implements aconstant voltage to constant current (CV-CC) transition and a constantcurrent to constant voltage (CC-CV) transition comprises: an amplifierA₀ having a first and second input and an output, said first inputconnects to feedback voltage (V_(FB)), said second input connects toreference voltage (V_(REF)), said amplifier A₀ having a pseudo-constantbias (PCB) which automatically biases and controls the transconductanceof amplifier A₀ as a function of an operating mode and connecting withan adaptive compensation network (ACN) which adaptively alters speed andstability for current regulation; a series-pass device responsive tosaid amplifier A₀ output and to second supply voltage (VDD₂) and havinga first output current (I_(OUT)) output and having a second outputcurrent (I_(SEN)) output, said series-pass device controlling thecurrent from VDD₂ to I_(OUT) and I_(SEN); a feedback network having twoinputs which sense voltage differential between output voltage (V_(OUT))and ground and generates an output V_(FB) to amplifier A₀; and aconstant current (CC) controller having a trans-impedence amplifier Z₁and a transconductance device Gm₁ and a first input I_(SEN) from theseries-pass device and a second input I_(REF) wherein amplifier Z₁compares I_(SEN) and I_(REF) and generates V_(SEL) as voltage for asignal to ACN for amplifier A₀ and device Gm₁ generates a currentcontrol I_(SEL) to the PCB, wherein a voltage regulation loop to theamplifier A₀ comprises a series-pass device and a feedback network whichapplies V_(FB) to said amplifier A₀ and a current regulation loopcomprises the series-pass device, the feedback network and the CCcontroller which applies an a control current (I_(SEL)) to said PCB anda voltage control (V_(SEL)) to said ACN.
 2. The linear regulator ofclaim 1 wherein a buffer is interposed between the amplifier A₀ and theseries-pass device.
 3. The linear regulator circuit of claim 1, furthercomprising a compensation capacitor C_(C) disposed in the voltageregulation loop and the current regulation loop.
 4. The linear regulatorof claim 1, wherein in the constant voltage (CV) mode, V_(OUT) isregulated, and I_(SEN) is monitored by amplifier Z₁.
 5. The linearregulator of claim 1, further comprising a compensation capacitor C_(C)disposed in the constant voltage (CV) feedback loop and the CC feedbackloop and wherein when the regulator is in a CV mode, the compensationcapacitor C_(C) is reduced by ACN to preserve stability and in CC mode,the CC feedback loop dominates and the compensation capacitor C_(C) ismagnified by ACN for frequency compensation.
 6. The linear regulator ofclaim 1 wherein in the CC mode, I_(OUT) is regulated and V_(FB) ismonitored by PCB and when V_(FB) ramps up and approaches V_(REF), theregulator is triggered to implement a CC to CV mode transition.
 7. Thelinear regulator of claim 1 wherein V_(OUT) is regulated to beapproximately$V_{OUT} = {\left\{ \frac{{Gm}_{0} \times R_{0} \times {Gm}_{pass} \times R_{OUT}}{1 + {\beta \times {Gm}_{0} \times R_{0} \times {Gm}_{pass} \times R_{OUT}}} \right) \times V_{REF}}$where Gm₀ and R₀ are the transconductance and output impedance of A₀respectively, Gm_(pass) is the transconductance of series-pass device,R_(OUT) is impedance of output load and β is the scaling factor offeedback network.
 8. The linear regulator of claim 1 wherein I_(OUT) isregulated to be approximately$I_{OUT} = {\left\{ \frac{Z_{1} \times {Gm}_{1} \times R_{0} \times {Gm}_{pass} \times R_{OUT}}{1 + {M \times Z_{1} \times {Gm}_{1} \times R_{0} \times {Gm}_{pass} \times R_{OUT}}} \right) \times I_{REF}}$where Z₁ and Gm₁ is the trans-impedance gain and the transconductancegain of CC controller respectively, R₀ is output impedance of A₀,Gm_(pass) is transconductance of series-pass device and M is the scalingratio I_(OUT) to I_(SEN).
 9. A linear regulator which implements aconstant voltage to constant current (CV-CC) transition and a constantcurrent to constant voltage (CC-CV) transition comprises: an amplifierA₀ having a first and second input and an output, said first inputconnects to feedback voltage (V_(FB)), said second input connects toreference voltage (V_(REF)), said amplifier A₀ having a pseudo-constantbias (PCB) which automatically biases and controls transconductance ofamplifier A₀ as function of operating mode and having an adaptivecompensation network (ACN) which adaptively alters speed and stabilityfor current regulation; a buffer connected to the amplifier A₀ outputand having a buffer output; a series-pass device connected to saidbuffer output and to second supply voltage (VDD₂) and having a firstoutput current (I_(OUT)) output and having a second output current(I_(SEN)) output, said series-pass device controlling the current fromVDD₂ to I_(OUT) and I_(SEN); a feedback network having two inputs whichsenses voltage differential between output voltage (V_(OUT)) and groundand generates an output V_(FB) to amplifier A₀; and a constant current(CC) controller having a trans-impedence amplifier Z₁ and atransconductance device Gm₁ and a first input I_(SEN) from theseries-pass device and a second input I_(REF) wherein the amplifier Z₁compares I_(SEN) and reference current (I_(REF)) and generates voltagecontrol (V_(SEL)) as voltage for the signal to ACN for amplifier A₀ anddevice Gm₁ generates a current control (I_(SEL)) to the PCB.
 10. Thelinear regulator circuit of claim 9, wherein the series-pass device hasa current sensor.
 11. The linear regulator of claim 10, wherein in theconstant voltage (CV) mode V_(OUT) is regulated and I_(SEN) is monitoredby amplifier Z₁.
 12. The linear regulator of claim 10, wherein whenI_(SEN) is larger than I_(REF), the regulator undergoes a CV to CC modetransition.
 13. The linear regulator circuit of claim 9, wherein theseries-pass device comprises a component selected from the groupconsisting of a p-channel MOSFET, an n-channel MOSFET and a bipolarjunction transistor.
 14. The linear regulator circuit of claim 9,wherein a constant voltage (CV) feedback loop to amplifier A₀ operatesin a constant voltage (CV) mode and a CC feedback loop to amplifier A₀operates in a CC mode.
 15. The linear regulator circuit of claim 14,further comprising a compensation capacitor C_(C) disposed in the CVfeedback loop and the CC feedback loop and wherein when the regulator isin a CV mode, the compensation capacitor C_(C) is reduced by ACN topreserve stability and in CC mode, the CC feedback loop dominates andthe compensation capacitor C_(C) is magnified by ACN for frequencycompensation.
 16. A power management method for managing constantvoltage to constant current (CV-CC) and constant current to constantvoltage (CC-CV) transition modes in a circuit comprising: controlling aconstant voltage (CV) mode of operation by a first bias to an amplifierto control transconductance Gm₀ in the amplifier so that the amplifierhas a gain of Gm₀*R₀ to amplify the difference between feedback voltage(V_(FB)) and reference voltage (V_(REF)) wherein a CV feedback loopkeeps an output voltage (V_(OUT)) to a desired level; and controlling aconstant current (CC) mode of operation by a second bias to theamplifier so that for a second transconductance Gm₁ the amplifierprovides a gain Gm₁*R₀ to amplify the difference between second outputcurrent (I_(SEN)) and reference current (I_(REF)) wherein a CC feedbackloop provides output current (I_(OUT)) at a desired level.
 17. The powermanagement method of claim 16 further comprising operating the amplifierin a high gain region in CV and CC modes.
 18. The power managementmethod of claim 16 further comprising activating a compensation networkto the band width for the CC mode and disabling the compensation networkin the CV mode.
 19. The power management method of claim 16 furthercomprising in the CV mode regulating the output voltage (V_(OUT)) andamplifying the second output current I_(SEN) by an amplifier Z₁ suchthat when I_(SEN)>I_(REF), the CV mode transitions to a CC mode.
 20. Thepower management method of claim 16 wherein in the CC mode, theregulating the first output current (I_(OUT)) and monitoring the V_(FB)so that when V_(FB) ramps up and approaches V_(REF), the CC modetransitions to the CV mode.